TEMPERATURE-ADAPTIVE MANAGEMENT OF DDR MEMORY LATENCIES IN MODERN COMPUTING SYSTEMS
DOI:
https://doi.org/10.17721/2519-481X/2026/90-03Keywords:
random-access memory, DRAM, DDR4, DDR5, memory latency, timings, temperature-adaptive control, leakage current, refresh interval, computing performanceAbstract
To manage modern electronic computing devices and server complexes, a critical criterion is ensuring maximum throughput of the RAM subsystem at the lowest possible latency levels. Modern dynamic random-access memory of DDR4 and DDR5 standards operates at ultra-high clock frequencies, which inevitably leads to intensive heat dissipation inside semiconductor chips under sustained workloads. An increase in the temperature of silicon crystals exponentially accelerates differential leakage currents in microscopic DRAM memory cell capacitors. This phenomenon requires a significant reduction in the intervals between forced refresh cycles (tREFI) and, as a result, leads to a significant drop in the overall performance and throughput of the computing subsystem. This review and research article examines in detail the problems of thermal throttling in modern memory profiles and proposes a comprehensive concept of dynamic temperature-adaptive management of key latencies (timings) and refresh intervals. The proposed closed-loop hardware-software system dynamically monitors the SPD thermal telemetry and adjusts major and minor timings to safely boost performance by 5–12% at low thermal ranges while ensuring data integrity under heavy processing loads.
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